Xilinx SDAccel Training

ArrayFire is the exclusive Xilinx SDAccel™ Authorized Training Partner (ATP) for North America. Our SDAccel training courses help enable design teams to leverage Xilinx FPGAs for OpenCL application acceleration.

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Course Name
Developing and Optimizing Applications Using the OpenCL Framework for FPGAs

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Course Description

Learn how to develop new applications written in OpenCL, C/C++, and RTL in the SDAccel development environment for use on Xilinx FPGAs. Porting existing applications is also covered.

Training lectures and labs for this course will enable attendees to gain necessary skills to: identify parallel computing applications suitable for accelerating on FPGAs, understand how the FPGA architecture lends itself to parallel computing, write OpenCL programs for FPGAs, and utilize the SDAccel Development Environment.

This course also demonstrates how to debug and profile OpenCL code using the SDAccel development environment. In addition, you will also learn how to maximize performance and efficiently utilize FPGA resources.

Course Duration – 2 days

Price and Scheduling – Contact ArrayFire for quote and scheduling (Xilinx training credits accepted)

Who Should Attend? – Software and hardware developers who want to develop OpenCL, C/C++, and RTL applications in the SDAccel development environment

Prerequisites  Basic knowledge of C/C++

Software Tools  SDAccel development environment and common build tools

Hardware  Architecture: 7 series, UltraScale, UltraScale+

 

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n't ask for better individualized instruction than the environment I was fortunate enough to encounter. The instructor was able to completely focus on

Course Outline

Day 1
  • Introduction to OpenCL
  • Comparison of CPU, GPU, and FPGA Architectures
  • OpenCL Support for Xilinx FPGAs
  • FPGA Hardware Details
  • Introduction to the OpenCL API
  • Lab 1: Creating an OpenCL Program from Scratch
  • OpenCL Execution Model
  • Lab 2: Vector Addition
  • Memory Hierarchy
  • Profiling and Debugging
  • Lab 3: Pi by Monte Carlo Processes
  • Optimization
  • Lab 4: Maximizing Performance
  • Lab 5: Optimizing Kernels
Day 2
  • Using the SDAccel Development Environment: Coding, Compiling, Emulating, Profiling, and Debugging
  • Lab 6: Profiling and Debugging Using the SDAccel Development Environment GUI
  • Using Existing C/C++ Code as Kernels in OpenCL
  • Lab 7: Optimizing C/C++ Code for OpenCL
  • RTL IP as Kernels in OpenCL
  • Lab 8: Using an RTL Kernel
Lab Descriptions
  • Lab 1: Creating an OpenCL Program from Scratch – Provides an overview of OpenCL API, memory transfers, and kernel enqueuer operations.
  • Lab 2: Vector Addition – Learn how to execute parallel kernels.
  • Lab 3: Pi by Monte Carlo Processes – Implement the Pi by Monte Carlo processes.
  • Lab 4: Maximizing Performance – Use vector data types and increase bandwidth.
  • Lab 5: Optimizing Kernels – Use Loop Unrolling and Loop Pipelining.
  • Lab 6: Profiling and Debugging Using the SDAccel Development Environment GUI – Learn how to use interactive programming tools to improve performance and squash bugs.
  • Lab 7: Optimizing C/C++ Code for OpenCL – Convert existing C/C++ code into a kernel that can be used by OpenCL
  • Lab 8: Using an RTL Kernel – Learn how to use existing, highly optimized IP in a new OpenCL application.

 

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